Xen 4.8.3 running on BeagleBoard X-15 - problem with paging

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Xen 4.8.3 running on BeagleBoard X-15 - problem with paging

Iain Hunter

 

I have today tracked the paging problem down to a need to flush the TLBs before enabling the MMU. This was done via the TLBIALLH. At the moment I've done it in head.s

Iain

 

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Re: Xen 4.8.3 running on BeagleBoard X-15 - problem with paging

Julien Grall-3
Hello,

On 01/02/18 16:06, Iain Hunter wrote:
> I have today tracked the paging problem down to a need to flush the TLBs
> before enabling the MMU. This was done via the TLBIALLH. At the moment
> I've done it in head.s

Could you be more specific where you added the TLBIALLH?

Cheers,

--
Julien Grall

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Re: Xen 4.8.3 running on BeagleBoard X-15 - problem with paging

Iain Hunter
Hi Julian,
The patch I applied is below. I have no idea if it is AM572x/DRA7xx specific or just specific to the 2017.01 u-boot I was using.

From 36e6bc81803a002637c9b854f2694bc655679e85 Mon Sep 17 00:00:00 2001
From: Iain Hunter <[hidden email]>
Date: Thu, 1 Feb 2018 14:45:27 +0000
Subject: [PATCH] for AM572x need to flush TLBs before enabling MMU

---
 xen/arch/arm/arm32/head.S | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S
index 2df9a98..b153eeb 100644
--- a/xen/arch/arm/arm32/head.S
+++ b/xen/arch/arm/arm32/head.S
@@ -347,6 +347,17 @@ virtphys_clash:
         b     fail
 
 1:
+        /*
+         * Flush the TLB before enabling MMU
+         */
+        dsb                          /* Ensure any page table updates made above
+                                      * have occurred. */
+        isb
+        mov   r0, #1
+        mcr   CP32(r0, TLBIALLH)     /* Flush hypervisor TLB */
+        dsb                          /* Ensure completion of TLB flush */
+        isb
+       
         PRINT("- Turning on paging -\r\n")
 
         ldr   r1, =paging            /* Explicit vaddr, not RIP-relative */
@@ -391,6 +402,7 @@ paging:
         ldr   r11, =EARLY_UART_VIRTUAL_ADDRESS
 #endif
 
+
         /*
          * Flush the TLB in case the 1:1 mapping happens to clash with
          * the virtual addresses used by the fixmap or DTB.
--
2.7.4

Iain

On 15 February 2018 at 18:36, Julien Grall <[hidden email]> wrote:
Hello,

On 01/02/18 16:06, Iain Hunter wrote:
I have today tracked the paging problem down to a need to flush the TLBs before enabling the MMU. This was done via the TLBIALLH. At the moment I've done it in head.s

Could you be more specific where you added the TLBIALLH?

Cheers,

--
Julien Grall


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