[qemu-xen master] hw/intc/arm_gic: reserved register addresses are RAZ/WI

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[qemu-xen master] hw/intc/arm_gic: reserved register addresses are RAZ/WI

patchbot
commit 0af294d774a8fd7b79646d003124577f1798b585
Author:     Peter Maydell <[hidden email]>
AuthorDate: Thu Jan 11 13:25:40 2018 +0000
Commit:     Michael Roth <[hidden email]>
CommitDate: Thu Jan 11 15:10:57 2018 -0600

    hw/intc/arm_gic: reserved register addresses are RAZ/WI
   
    The GICv2 specification says that reserved register addresses
    must RAZ/WI; now that we implement external abort handling
    for Arm CPUs this means we must return MEMTX_OK rather than
    MEMTX_ERROR, to avoid generating a spurious guest data abort.
   
    Cc: [hidden email]
    Signed-off-by: Peter Maydell <[hidden email]>
    Message-id: [hidden email]
    Reviewed-by: Alistair Francis <[hidden email]>
    (cherry picked from commit 0cf09852015e47a5fbb974ff7ac320366afd21ee)
    Signed-off-by: Michael Roth <[hidden email]>
---
 hw/intc/arm_gic.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 5a0e2a3..d701e49 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -1261,7 +1261,8 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset,
     default:
         qemu_log_mask(LOG_GUEST_ERROR,
                       "gic_cpu_read: Bad offset %x\n", (int)offset);
-        return MEMTX_ERROR;
+        *data = 0;
+        break;
     }
     return MEMTX_OK;
 }
@@ -1329,7 +1330,7 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset,
     default:
         qemu_log_mask(LOG_GUEST_ERROR,
                       "gic_cpu_write: Bad offset %x\n", (int)offset);
-        return MEMTX_ERROR;
+        return MEMTX_OK;
     }
     gic_update(s);
     return MEMTX_OK;
--
generated by git-patchbot for /home/xen/git/qemu-xen.git#master

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