Author: Andrew Cooper <[hidden email]>
AuthorDate: Mon Jul 30 11:22:42 2018 +0200
Commit: Jan Beulich <[hidden email]>
CommitDate: Mon Jul 30 11:22:42 2018 +0200
x86/svm Fixes and cleanup to svm_inject_event()
* State adjustments (and debug tracing) for #DB/#BP/#PF should not be done
for `int $n` instructions. Updates to %cr2 occur even if the exception
combines to #DF.
* Don't opencode DR_STEP when updating %dr6.
* Simplify the logic for calling svm_emul_swint_injection() as in the common
case, every condition needs checking.
* Fix comments which have become stale as code has moved between components.
Signed-off-by: Andrew Cooper <[hidden email]>
Reviewed-by: Jan Beulich <[hidden email]>
Reviewed-by: Boris Ostrovsky <[hidden email]>
master commit: 8dab867c81ede455009028a9a88edc4ff3b9da88
master date: 2018-07-17 10:12:40 +0100
xen/arch/x86/hvm/svm/svm.c | 41 +++++++++++++++++------------------------
1 file changed, 17 insertions(+), 24 deletions(-)
diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c
index 165500e3f2..b964c59dad 100644
@@ -1432,24 +1432,18 @@ static void svm_inject_event(const struct x86_event *event)
* Xen must emulate enough of the event injection to be sure that a
* further fault shouldn't occur during delivery. This covers the fact
* that hardware doesn't perform DPL checking on injection.
- * Also, it accounts for proper positioning of %rip for an event with trap
- * semantics (where %rip should point after the instruction) which suffers
- * a fault during injection (at which point %rip should point at the
- * instruction).
if ( event->type == X86_EVENTTYPE_PRI_SW_EXCEPTION ||
- (!cpu_has_svm_nrips && (event->type == X86_EVENTTYPE_SW_INTERRUPT ||
- event->type == X86_EVENTTYPE_SW_EXCEPTION)) )
+ (!cpu_has_svm_nrips && (event->type >= X86_EVENTTYPE_SW_INTERRUPT)) )
- switch ( _event.vector )
+ switch ( _event.vector | -(_event.type == X86_EVENTTYPE_SW_INTERRUPT) )
if ( regs->eflags & X86_EFLAGS_TF )
- vmcb_set_dr6(vmcb, vmcb_get_dr6(vmcb) | 0x4000);
+ vmcb_set_dr6(vmcb, vmcb_get_dr6(vmcb) | DR_STEP);
/* fall through */
@@ -1459,6 +1453,13 @@ static void svm_inject_event(const struct x86_event *event)
+ case TRAP_page_fault:
+ ASSERT(_event.type == X86_EVENTTYPE_HW_EXCEPTION);
+ curr->arch.hvm_vcpu.guest_cr = _event.cr2;
+ vmcb_set_cr2(vmcb, _event.cr2);
if ( unlikely(eventinj.fields.v) &&
@@ -1481,13 +1482,9 @@ static void svm_inject_event(const struct x86_event *event)
* icebp, software events with trap semantics need emulating, so %rip in
* the trap frame points after the instruction.
- * The x86 emulator (if requested by the x86_swint_emulate_* choice) will
- * have performed checks such as presence/dpl/etc and believes that the
- * event injection will succeed without faulting.
- * The x86 emulator will always provide fault semantics for software
- * events, with _trap.insn_len set appropriately. If the injection
- * requires emulation, move %rip forwards at this point.
+ * svm_emul_swint_injection() has already confirmed that events with trap
+ * semantics won't fault on injection. Position %rip/NextRIP suitably,
+ * and restrict the event type to what hardware will tolerate.
switch ( _event.type )
@@ -1544,16 +1541,12 @@ static void svm_inject_event(const struct x86_event *event)
eventinj.fields.errorcode == (uint16_t)eventinj.fields.errorcode);
vmcb->eventinj = eventinj;
- if ( _event.vector == TRAP_page_fault )
- curr->arch.hvm_vcpu.guest_cr = _event.cr2;
- vmcb_set_cr2(vmcb, _event.cr2);
- HVMTRACE_LONG_2D(PF_INJECT, _event.error_code, TRC_PAR_LONG(_event.cr2));
+ if ( _event.vector == TRAP_page_fault &&
+ _event.type == X86_EVENTTYPE_HW_EXCEPTION )
+ HVMTRACE_LONG_2D(PF_INJECT, _event.error_code,
HVMTRACE_2D(INJ_EXC, _event.vector, _event.error_code);
static int svm_event_pending(struct vcpu *v)
generated by git-patchbot for /home/xen/git/xen.git#stable-4.11
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