[xen stable-4.9] x86: avoid #GP for PV guest MSR accesses

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[xen stable-4.9] x86: avoid #GP for PV guest MSR accesses

patchbot
commit cfdd991ff3311734b59373b7cb74f9e4abc8dfbd
Author:     Jan Beulich <[hidden email]>
AuthorDate: Tue Oct 24 16:14:50 2017 +0200
Commit:     Jan Beulich <[hidden email]>
CommitDate: Tue Oct 24 16:14:50 2017 +0200

    x86: avoid #GP for PV guest MSR accesses
   
    Halfway recent Linux kernels probe MISC_FEATURES_ENABLES on all CPUs,
    leading to ugly recovered #GP fault messages with debug builds on older
    systems. We can do better, so introduce synthetic feature flags for
    both this and PLATFORM_INFO to avoid the rdmsr_safe() altogether.
   
    Note that the r/o nature of PLATFORM_INFO is now also being enforced.
   
    The rdmsr_safe() uses for MISC_ENABLE are left in place as benign - it
    exists for all 64-bit capable Intel CPUs (see e.g. early_init_intel()).
   
    Signed-off-by: Jan Beulich <[hidden email]>
    Acked-by: Andrew Cooper <[hidden email]>
---
 xen/arch/x86/cpu/intel.c          | 13 +++++++++++--
 xen/arch/x86/traps.c              | 17 ++++++-----------
 xen/include/asm-x86/cpufeatures.h |  2 ++
 3 files changed, 19 insertions(+), 13 deletions(-)

diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c
index 6a41334..a7c0d49 100644
--- a/xen/arch/x86/cpu/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -21,10 +21,19 @@ static bool __init probe_intel_cpuid_faulting(void)
 {
  uint64_t x;
 
- if (rdmsr_safe(MSR_INTEL_PLATFORM_INFO, x) ||
-    !(x & MSR_PLATFORM_INFO_CPUID_FAULTING))
+ if (rdmsr_safe(MSR_INTEL_PLATFORM_INFO, x))
  return 0;
 
+ setup_force_cpu_cap(X86_FEATURE_MSR_PLATFORM_INFO);
+
+ if (!(x & MSR_PLATFORM_INFO_CPUID_FAULTING)) {
+ if (!rdmsr_safe(MSR_INTEL_MISC_FEATURES_ENABLES, x))
+ setup_force_cpu_cap(X86_FEATURE_MSR_MISC_FEATURES);
+ return 0;
+ }
+
+ setup_force_cpu_cap(X86_FEATURE_MSR_MISC_FEATURES);
+
  expected_levelling_cap |= LCAP_faulting;
  levelling_caps |=  LCAP_faulting;
  setup_force_cpu_cap(X86_FEATURE_CPUID_FAULTING);
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index e66245a..a3e8504 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -2626,8 +2626,7 @@ static int priv_op_read_msr(unsigned int reg, uint64_t *val,
         return X86EMUL_OKAY;
 
     case MSR_INTEL_PLATFORM_INFO:
-        if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
-             rdmsr_safe(MSR_INTEL_PLATFORM_INFO, *val) )
+        if ( !boot_cpu_has(X86_FEATURE_MSR_PLATFORM_INFO) )
             break;
         *val = 0;
         if ( this_cpu(cpuid_faulting_enabled) )
@@ -2635,8 +2634,7 @@ static int priv_op_read_msr(unsigned int reg, uint64_t *val,
         return X86EMUL_OKAY;
 
     case MSR_INTEL_MISC_FEATURES_ENABLES:
-        if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
-             rdmsr_safe(MSR_INTEL_MISC_FEATURES_ENABLES, *val) )
+        if ( !boot_cpu_has(X86_FEATURE_MSR_MISC_FEATURES) )
             break;
         *val = 0;
         if ( curr->arch.cpuid_faulting )
@@ -2834,15 +2832,12 @@ static int priv_op_write_msr(unsigned int reg, uint64_t val,
         return X86EMUL_OKAY;
 
     case MSR_INTEL_PLATFORM_INFO:
-        if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
-             val || rdmsr_safe(MSR_INTEL_PLATFORM_INFO, val) )
-            break;
-        return X86EMUL_OKAY;
+        /* The MSR is read-only. */
+        break;
 
     case MSR_INTEL_MISC_FEATURES_ENABLES:
-        if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
-             (val & ~MSR_MISC_FEATURES_CPUID_FAULTING) ||
-             rdmsr_safe(MSR_INTEL_MISC_FEATURES_ENABLES, temp) )
+        if ( !boot_cpu_has(X86_FEATURE_MSR_MISC_FEATURES) ||
+             (val & ~MSR_MISC_FEATURES_CPUID_FAULTING) )
             break;
         if ( (val & MSR_MISC_FEATURES_CPUID_FAULTING) &&
              !this_cpu(cpuid_faulting_enabled) )
diff --git a/xen/include/asm-x86/cpufeatures.h b/xen/include/asm-x86/cpufeatures.h
index bc98227..3fa9b0a 100644
--- a/xen/include/asm-x86/cpufeatures.h
+++ b/xen/include/asm-x86/cpufeatures.h
@@ -22,3 +22,5 @@ XEN_CPUFEATURE(APERFMPERF,      (FSCAPINTS+0)*32+ 8) /* APERFMPERF */
 XEN_CPUFEATURE(MFENCE_RDTSC,    (FSCAPINTS+0)*32+ 9) /* MFENCE synchronizes RDTSC */
 XEN_CPUFEATURE(XEN_SMEP,        (FSCAPINTS+0)*32+10) /* SMEP gets used by Xen itself */
 XEN_CPUFEATURE(XEN_SMAP,        (FSCAPINTS+0)*32+11) /* SMAP gets used by Xen itself */
+XEN_CPUFEATURE(MSR_PLATFORM_INFO, (FSCAPINTS+0)*32+12) /* PLATFORM_INFO MSR present */
+XEN_CPUFEATURE(MSR_MISC_FEATURES, (FSCAPINTS+0)*32+13) /* MISC_FEATURES_ENABLES MSR present */
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.9

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