[xen staging-4.6] x86/traps: Fix %dr6 handing in #DB handler
Author: Andrew Cooper <[hidden email]>
AuthorDate: Tue May 8 18:28:03 2018 +0100
Commit: Andrew Cooper <[hidden email]>
CommitDate: Tue May 8 18:28:03 2018 +0100
x86/traps: Fix %dr6 handing in #DB handler
Most bits in %dr6 accumulate, rather than being set directly based on the
current source of #DB. Have the handler follow the manuals guidance, which
avoids leaking hypervisor debugging activities into guest context.
This is part of XSA-260 / CVE-2018-8897.
Signed-off-by: Andrew Cooper <[hidden email]>
Reviewed-by: Jan Beulich <[hidden email]>
xen/arch/x86/traps.c | 28 +++++++++++++++++++++++++++-
xen/include/asm-x86/debugreg.h | 2 ++
2 files changed, 29 insertions(+), 1 deletion(-)
+ /* Stash dr6 as early as possible. */
+ dr6 = read_debugreg(6);
+ * At the time of writing (March 2018), on the subject of %dr6:
+ * The Intel manual says:
+ * Certain debug exceptions may clear bits 0-3. The remaining contents
+ * of the DR6 register are never cleared by the processor. To avoid
+ * confusion in identifying debug exceptions, debug handlers should
+ * clear the register (except bit 16, which they should set) before
+ * returning to the interrupted task.
+ * The AMD manual says:
+ * Bits 15:13 of the DR6 register are not cleared by the processor and
+ * must be cleared by software after the contents have been read.
+ * Some bits are reserved set, some are reserved clear, and some bits
+ * which were previously reserved set are reused and cleared by hardware.
+ * For future compatibility, reset to the default value, which will allow
+ * us to spot any bit being changed by hardware to its non-default value.
+ write_debugreg(6, X86_DR6_DEFAULT);
if ( !guest_mode(regs) )
if ( regs->eflags & X86_EFLAGS_TF )
@@ -3705,7 +3730,8 @@ void do_debug(struct cpu_user_regs *regs)
/* Save debug status register where guest OS can peek at it */
- v->arch.debugreg = read_debugreg(6);
+ v->arch.debugreg |= (dr6 & ~X86_DR6_DEFAULT);
+ v->arch.debugreg &= (dr6 | ~X86_DR6_DEFAULT);
do_guest_trap(TRAP_debug, regs, 0);
diff --git a/xen/include/asm-x86/debugreg.h b/xen/include/asm-x86/debugreg.h
index c57914efc6..b3b10eaf40 100644
@@ -24,6 +24,8 @@
#define DR_STATUS_RESERVED_ZERO (~0xffffeffful) /* Reserved, read as zero */
#define DR_STATUS_RESERVED_ONE 0xffff0ff0ul /* Reserved, read as one */
+#define X86_DR6_DEFAULT 0xffff0ff0ul /* Default %dr6 value. */
/* Now define a bunch of things for manipulating the control register.
The top two bytes of the control register consist of 4 fields of 4
bits - each field corresponds to one of the four debug registers,
generated by git-patchbot for /home/xen/git/xen.git#staging-4.6