[xen-unstable] x86_emulate: Emulate RDTSC instruction.

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[xen-unstable] x86_emulate: Emulate RDTSC instruction.

Xen patchbot-unstable
# HG changeset patch
# User Keir Fraser <[hidden email]>
# Date 1196253886 0
# Node ID 43b7d24acf9c05d557fd0623ab6e495e630cf0d0
# Parent  cca2f2fb857d5dce7c435e92b8fc105d388f4f5d
x86_emulate: Emulate RDTSC instruction.
Signed-off-by: Keir Fraser <[hidden email]>
---
 xen/arch/x86/x86_emulate.c |   26 ++++++++++++++++++++++++--
 1 files changed, 24 insertions(+), 2 deletions(-)

diff -r cca2f2fb857d -r 43b7d24acf9c xen/arch/x86/x86_emulate.c
--- a/xen/arch/x86/x86_emulate.c Wed Nov 28 12:44:19 2007 +0000
+++ b/xen/arch/x86/x86_emulate.c Wed Nov 28 12:44:46 2007 +0000
@@ -191,7 +191,7 @@ static uint8_t twobyte_table[256] = {
     /* 0x28 - 0x2F */
     0, 0, 0, 0, 0, 0, 0, 0,
     /* 0x30 - 0x37 */
-    ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0,
+    ImplicitOps, ImplicitOps, ImplicitOps, 0, 0, 0, 0, 0,
     /* 0x38 - 0x3F */
     0, 0, 0, 0, 0, 0, 0, 0,
     /* 0x40 - 0x47 */
@@ -270,6 +270,13 @@ struct operand {
         } mem;
     };
 };
+
+/* MSRs. */
+#define MSR_TSC   0x10
+
+/* Control register flags. */
+#define CR0_PE    (1<<0)
+#define CR4_TSD   (1<<2)
 
 /* EFLAGS bit definitions. */
 #define EFLG_VIP  (1<<20)
@@ -739,7 +746,7 @@ in_realmode(
         return 0;
 
     rc = ops->read_cr(0, &cr0, ctxt);
-    return (!rc && !(cr0 & 1));
+    return (!rc && !(cr0 & CR0_PE));
 }
 
 static int
@@ -2860,6 +2867,21 @@ x86_emulate(
         break;
     }
 
+    case 0x31: /* rdtsc */ {
+        unsigned long cr4;
+        uint64_t val;
+        fail_if(ops->read_cr == NULL);
+        if ( (rc = ops->read_cr(4, &cr4, ctxt)) )
+            goto done;
+        generate_exception_if((cr4 & CR4_TSD) && !mode_ring0(), EXC_GP);
+        fail_if(ops->read_msr == NULL);
+        if ( (rc = ops->read_msr(MSR_TSC, &val, ctxt)) != 0 )
+            goto done;
+        _regs.edx = (uint32_t)(val >> 32);
+        _regs.eax = (uint32_t)(val >>  0);
+        break;
+    }
+
     case 0x32: /* rdmsr */ {
         uint64_t val;
         generate_exception_if(!mode_ring0(), EXC_GP);

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